v1.0 - Latest Release

Open-source FMCW radar
signal processing.

OPERA-DSP is a hardware IP library for FMCW radar DSP - built with Chisel, providing essential cores for windowing, FFT, magnitude computation, and CFAR detection. Apache-2.0 Licensed.

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📡

PreProcessing

Formats raw ADC data from FMCW radar sensors, ensuring compatibility with downstream DSP blocks. AXI4 & TileLink interfaces.

〰️

Windowing

Applies window functions before FFT to reduce spectral leakage. Supports AXI4 and TileLink variants with configurable parameters.

FFT

Fast Fourier Transform core for converting time-domain radar signals to frequency domain.

📊

Magnitude

Computes magnitude of complex signals - supports squared magnitude, JPL approximation, and log2 computation.

🎯

CFAR Detection

Constant False Alarm Rate detection for reliable target identification in varying noise conditions.

🔧

Chisel-Based

Built on Chisel HDL with Scala - enabling parameterized, type-safe hardware generation with modern software practices.

terminal
# Clone the repository
$ 
$ cd opera-dsp

# Clone required submodules (rocket-chip, dsptools, rocket-dsp-utils)
$ make clone_dependencies

# Generate AXI4 RTL for a block
$ make rtl_preprocessing_axi4
$ make rtl_windowing_axi4
$ make rtl_magnitude_axi4
$ make rtl_fft_axi4
$ make rtl_cfar_axi4

# Generate TileLink RTL for a block
$ make rtl_preprocessing_tl
$ make rtl_windowing_tl
$ make rtl_magnitude_tl
$ make rtl_fft_tl
$ make rtl_cfar_tl

# Run focused wrapper tests
$ make test_preprocessing
$ make test_windowing_functions_axi4
$ make test_windowing_functions_tl
$ make test_magnitude_axi4
$ make test_magnitude_tl
$ make test_fft_axi4
$ make test_fft_tl
$ make test_cfar_axi4
$ make test_cfar_tl
Chisel Hardware construction language
Scala / SBT Build system & language
Verilator Simulation & testing
Sphinx Documentation generation

This project was funded through the NGI0 Core Fund, a fund established by NLnet with financial support from the European Commission's Next Generation Internet programme, under the aegis of DG Communications Networks, Content and Technology under grant agreement No 101092990.

Start building with OPERA-DSP

Explore the docs, try the IP cores, or contribute to the project.